Generally, a clock signal has been used as a reference signal which is synchronized with an operation timing in a system or an electronic circuit and this clock signal has been used for high-speed performance of an integrated circuit without an error. When a clock signal from an external circuit is used in an internal circuit, a delay of the clock signal, which is said “clock skew”, is generated in the internal circuit. To prevent this skew in the internal circuit, a DLL to synchronize an internal clock signal with an external clock signal has been employed.
On the other hand, as compared with a conventional phase locked loop (PLL), the DLL has a merit in that it has an effect on the noise so that the DLL has been used in SDRAMs (Synchronous DRAM) and DDR SDRAMs (Double Data Rate Synchronous DRAM). A register controlled DLL, which is digitally done in controlling its phase, has been widely used. The register controlled DLL in the Synchronous DRAM compensates for a delay time of an internal clock signal, which is produced by an external clock signal, and makes data output signal synchronized with the external clock signal by reflecting a negative delay time on the internal clock signal path.
Referring to FIG. 1, a register controlled DLL of a conventional DDR SDRAM includes a clock buffer 10, a clock divider 11, a phase comparator 16, a delay line 12, a dummy delay line 13, a shift register 17, a shift register controller 18, a DLL driver 14, and a delay model 15. The clock buffer 10 buffers an external clock signal CLK and generates a source clock signal clk which is synchronized with a rising or falling edge of the external clock signal CLK. The clock divider 11 divides the source clock signal clk into M (integer, typically M=8) divided clock signals and generates a monitoring clock signal fb_div and a reference clock signal ref. The delay line 12, which includes a plurality of programmable unit delayers, receives the source clock signal clk from the clock buffer 10. The dummy delay line 13 having the same structure as the delay line 12 also includes a plurality of programmable unit delayers. The shift register 17 determines an amount of delay time in both the delay line 12 and the dummy delay line 13 and the delay model 15 delays the delay signal from the dummy delay line 13 using the actually same delay path of the source clock signal clk. The phase comparator 16 compares the reference clock signal ref from the clock divider 11 with a feedback clock signal fb_dm and the shift register controller 18 controls the shift register 17 in response to the comparison signal from the phase comparator 16 in order that the shift register 17 determines the delay amount of the delay line 12 and the dummy delay line 13. It should be noted that the delay model 15 includes the same delay path as the clock buffer 10 and a data output buffer (not shown).
The clock divider 11 produces M divided clock signals using the source clock signal clk in order to generate the monitoring clock signal fb_div and the reference clock signal ref. Accordingly, the monitoring clock signal fb_div and the reference clock signal ref are synchronized with an M-th external clock signal CLK. Typically, the monitoring clock signal fb_div and the reference clock signal ref are out of phase; however, this phase difference is not inevitably required in the register controlled DLL. The clock divider 11 is employed to reduce the power consumption of the DLL and to avoid the complexity of a control logic circuit to be required with the increase of operating frequency. Accordingly, it is possible to remove the clock divider 11 from the DLL if such a requirement is not wanted.
In the DLL using the shift register, the delay monitoring clock signal fb_div passes through one of the unit delayer in the dummy delay line 13 and is also delayed by a predetermined amount of delay time in the delay model 15. The comparator 16 compares a rising edge of the reference clock signal ref with a rising edge of the feedback clock signal fb_dm from the delay model 15 and the shift register controller 18 outputs shift control signals SR (shift right) and SL (shift left) to controls the shift register 17 in response to a comparison signal from the comparator 16.
The shift register 17 enables one of unit delayers in the delay line 12 and the dummy delay line 13 in response to the shift control signals SR and SL in order to determine an amount of delay time in the delay line 12 and the dummy delay line 13. At this time, when the shift control signal SR is activated, the shift registers shifts an input bit signal to the right one-by-one and when the shift control signal SL is activated, the shift registers shifts an input bit signal to the left one-by-one. A locking operation is achieved when the comparison of the reference clock signal ref and the feedback clock signal fb_dm has a minimum jitter. When the DLL is locked, a locking signal (not shown) is issued therein and the DLL driver 14 outputs a DLL clock signal clk_dll which is newly generated and is synchronized with the external clock signal CLK.
Referring to FIG. 2, the delay line 12 includes n unit delayers UD1 to UDn which are in series coupled to each other. Each of the unit delayers includes a first NAND gate NAND100 receiving an input clock signal clk_in and one of delay selection signals Reg_1 to Reg_n from the shift register 17, a second NAND gate NAND 101 receiving an output signal of the first NAND gate NAND100 and an output signal of a previous unit delayer, and an inverter INV100 inverting an output signal of the second NAND gate NAND 101. The first unit delayer UD1 is coupled to a power supply VDD because there is no previously delayed signal.
For example, in the unit delayer UD4, in case that the delay selection signal Reg_3 is in a high voltage level, the firat NAND gate NAND100 is enabled and the input clock signal clk_in is inverted. As a result, the second NAND gate NAND 101 and the inverter INV100 delay the input clock signal clk_in. In case that the delay selection signal Reg_3 is in a low voltage level, the firat NAND gate NAND100 is disenabled and the input clock signal clk_in is blocked. As a result, an output signal of the first NAND gate NAND 100 is in a high voltage level and the second NAND gate NAND 101 and the inverter INV100 delay an output signal from the previous unit delayer UD3 for a predetermined time.
Referring to FIG. 3, the shifter register 22 is made up of n stages. Only four stages are shown In FIG. 3 and only one stage to produce a delay selection signal Reg_2 will be illustrated. Each of the stages includes a latch circuit L consisting of a NAND gate NAND102 and an inverter INV101, a switching part S for selecting one from the latched values in response to shift signals sre, sro, slo, sle, and a logic combiner C for logically combining a positive output signal (Q) of the latch circuit L in a current stage and a negative output signal (/Q) of an latch circuit L in the previous stage. In the latch circuit L, the AND gate NAND102 receives a reset signal resetb, as an initial signal, and an inverted signal /Q and an inverter INV101 receives an output signal of the NAND gate NAND102 and outputs the inverted signal (/Q) to the NAND gate NAND102. At the initialization, the positive output signals (Q) of all the latch circuits are in a high voltage level.
The switching part S includes: an NMOS transistor M4, which is connected to a positive output terminal of the latch circuit L, having a gate receiving a negative output signal (/Q) of the latch circuit L in the previous stage; an NMOS transistor M3, which is connected to a negative output terminal of the latch circuit L, having a gate receiving a negative output signal (/Q) of the latch circuit L in the next stage; an NMOS transistor M1 to selectively connect the negative output terminal of the latch circuit L to a ground voltage level in response to an odd shift-right signal sro together with the NMOS transistor M3; and an NMOS transistor M2 to selectively connect the positive output terminal of the latch circuit L to a ground voltage level in response to an even shift-left signal slo together with the NMOS transistor M4. The switching parts S in the previous and next stages are controlled by both an even shift-right signal sre and an odd shift-left signal slo of the shift signals sre, sro, slo and sle.
The logic combiner C has a NAND gate NAND103 receiving both the positive output signal (Q) of the latch circuit L in the current stage and the negative output signal (/Q) of the latch circuit L in the previous stage and an inverter INV102 to receive and invert an output signal of the NAND gate NAND103. In the shifter register 22, latched values of all the stages are, at the initial operation, in a high voltage level by a reset signal resetb and the delay selection signals Reg_1, Reg_2, . . . , Reg_n are 1, 0, . . . , 0, respectively. Even if the continuous shift operations are carried out, one of the delay selection signals Reg_1 to Reg_n is in a high voltage level. Accordingly, in the delay line of FIG. 2, one of the unit delayers is enabled and the input clock signal clk_in is inputted into only one enabled unit delayer. As a result, other unit delayers are served as a load.
FIG. 4 is a schematic view illustrating the conventional shift register and the delay line. Referring to FIG. 4, if the delay selection signal Reg_7 from the shift register 17 is in a high voltage level and the others are in a low voltage level, the seventh unit delayer UD7, which are positioned in both the delay line 12 and the dummy delay line 13, are enabled. Accordingly, the source clock signal clk and the delay monitoring clock fb_div are inputted into the seventh unit delayer UD7, thereby passing through the delay line 12 and the dummy delay line 13. In this case, other unit delayers, except for the seventh unit delayers UD7, are served as a load of the source clock signal clk and the delay monitoring clock fb_div because all of other delay selection signals are in a low voltage level.
In the 256M DDR SDRAM, the power consumption caused by this load leads the current loss of 2 to 4 mA at the normal operation region of 100 to 200 MHz. The register controlled DLL in the synchronous memory devices is considerably associated with data output operation. For example, since the conventional register DLL drives the delay line beside the read operation, the more power consumption is caused in the conventional register controlled DLL.
Further to the above-mentioned power consumption, the conventional register controlled DLL has a drawback in the signal integrity. That is, since the clock buffer drives a large load, the output signal of the clock buffer may be fluctuated considerably according to the variation of the power supply voltage. These problems appear in other digital DLL as well as the above-mentioned register controlled DLL.